`include "common_defines.v"
module CPU(
  input clk,
  input rst_n,
  // 用户定义的可屏蔽中断 不影响核心运行的中断
  input user_interrupt,
  // 不可屏蔽的关键中断 例如 UPS断电信号 核心外设错误信号
  input sys_interrupt,
  /* AXI Master */
  /* AR  */
  input                               axi_ar_ready  ,
  output                              axi_ar_valid  ,
  output [`AXI_ADDR_WIDTH-1:0]        axi_ar_addr   ,
  output [2:0]                        axi_ar_prot   ,
  output [`AXI_ID_WIDTH-1:0]          axi_ar_id     ,
  output [`AXI_USER_WIDTH-1:0]        axi_ar_user   ,
  output [7:0]                        axi_ar_len    ,
  output [2:0]                        axi_ar_size   ,
  output [1:0]                        axi_ar_burst  ,
  output                              axi_ar_lock   ,
  output [3:0]                        axi_ar_cache  ,
  output [3:0]                        axi_ar_qos    ,
  /* R */
  output                              axi_r_ready   ,
  input                               axi_r_valid   ,
  input  [1:0]                        axi_r_resp    ,
  input  [`AXI_DATA_WIDTH-1:0]        axi_r_data    ,
  input                               axi_r_last    ,
  input  [`AXI_ID_WIDTH-1:0]          axi_r_id      ,
  input  [`AXI_USER_WIDTH-1:0]        axi_r_user    ,
  /* AW */
  input                               axi_aw_ready  ,       
  output                              axi_aw_valid  ,   
  output [`AXI_ADDR_WIDTH-1:0]        axi_aw_addr   ,   
  output [2:0]                        axi_aw_prot   ,   
  output [`AXI_ID_WIDTH-1:0]          axi_aw_id     ,
  output [`AXI_USER_WIDTH-1:0]        axi_aw_user   ,     
  output [7:0]                        axi_aw_len    ,      
  output [2:0]                        axi_aw_size   ,
  output [1:0]                        axi_aw_burst  ,
  output                              axi_aw_lock   ,   
  output [3:0]                        axi_aw_cache  ,   
  output [3:0]                        axi_aw_qos    ,   
  /* W */
  input                               axi_w_ready   ,  
  output                              axi_w_valid   ,
  output [`AXI_DATA_WIDTH-1:0]        axi_w_data    ,   
  output [`AXI_DATA_WIDTH/8-1:0]      axi_w_strb    ,   
  output                              axi_w_last    ,   
  /* B */
  output                              axi_b_ready   ,
  input                               axi_b_valid   ,
  input  [1:0]                        axi_b_resp    ,  
  input  [`AXI_ID_WIDTH-1:0]          axi_b_id      ,
  input  [`AXI_USER_WIDTH-1:0]        axi_b_user      
);

wire [63:0] taxi_r_data;
ysyx_210232_Core rena_v1_core ( // @[SOCTop.scala 54:22]
    .clock(clk),
    .reset(~rst_n),
    .io_axi_aw_ready    (axi_aw_ready ),
    .io_axi_aw_valid    (axi_aw_valid ),
    .io_axi_aw_bits_addr(axi_aw_addr  ),
    .io_axi_aw_bits_size(axi_aw_size  ),
    .io_axi_w_ready     (axi_w_ready  ),
    .io_axi_w_valid     (axi_w_valid  ),
    .io_axi_w_bits_data (axi_w_data   ),
    .io_axi_w_bits_strb (axi_w_strb   ),
    .io_axi_b_ready     (axi_b_ready  ),
    .io_axi_b_valid     (axi_b_valid  ),
    .io_axi_b_bits_id   (axi_b_id     ),
    .io_axi_b_bits_resp (    ),
    .io_axi_ar_ready    (axi_ar_ready ),
    .io_axi_ar_valid    (axi_ar_valid ),
    .io_axi_ar_bits_id  (axi_ar_id    ),
    .io_axi_ar_bits_addr(axi_ar_addr  ),
    .io_axi_ar_bits_size(axi_ar_size  ),
    .io_axi_r_ready     (axi_r_ready  ),
    .io_axi_r_valid     (axi_r_valid  ),
    .io_axi_r_bits_id   (axi_r_id     ),
    .io_axi_r_bits_data (taxi_r_data   ),
    .io_axi_r_bits_resp (axi_r_resp   ),
    .io_axi_r_bits_last (axi_r_last   )
  );
reg [31:0] addrR;
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    addrR <= 'd0;
  else if(axi_ar_valid && axi_ar_ready)
    addrR <= axi_ar_addr;

assign taxi_r_data = (axi_r_id == 'd2) ? axi_r_data : (addrR[2] ? {32'd0,axi_r_data[63:32]} : axi_r_data);

assign axi_aw_prot  = 'd0;
assign axi_aw_id    = 'd0;
assign axi_aw_user  = 'd0;
assign axi_aw_len   = 'd0;
assign axi_aw_burst = 'd0;
assign axi_aw_lock  = 'd0;
assign axi_aw_cache = 'd0;
assign axi_aw_qos   = 'd0;

assign axi_ar_prot  = 'd0;
assign axi_ar_user  = 'd0;
assign axi_ar_len   = 'd0;
assign axi_ar_burst = 'd0;
assign axi_ar_lock  = 'd0;
assign axi_ar_cache = 'd0;
assign axi_ar_qos   = 'd0;
assign axi_r_user   = 'd0;
assign axi_w_last   = 'd1;
assign axi_b_user   = 'd0;

endmodule